Wednesday, March 19, 2014

Altera - FPGA CPLD Structured ASIC

Altera is one of the pioneers of Programmable Logic, following notable early leaders Signetics and MMI in introducing PLDs.

Altera - FPGA CPLD Structured ASIC 

Altera develops many features that are geared towards system-on-a-programmable-chip (SOPC) capability. Some of the more recent examples include embedded memory, embedded processors, and high-speed transceivers.

MAX 10 FPGAs are built on TSMC’s 55 nm embedded NOR flash technology, enabling instant-on functionality. Integrated features include analog-to-digital converters (ADCs) and dual configuration flash allowing you to store and dynamically switch between two images on a single chip.

Altera 10M08 Evaluation kit

Highlights -

Analog blocks—Integrated analog blocks with ADCs and temperature sensor provide lower latency and reduced board space with more flexible sample-sequencing.

DSP blocks—As the first non-volatile FPGA with DSP, MAX 10 FPGAs are ideal for high-performance, high-precision applications using integrated 18x18 multipliers.

Altera 10M08 Evaluation kit provides easy access to the FPGA's I/O and ADC block and interfaces to potentiometer, LEDs, push-buttons, switches and several different connectors for expansion.

Altera Corporation
101 Innovation Drive San Jose, CA 95134, USA

Updated May 2015

Blocks

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